1. Field of the Invention
The present application relates to the field of electronics, and more particularly, to methods of forming electronic component packages and related structures.
2. Description of the Related Art
Fine pitch flip chip technology requires very tight pad to pad spacing on the substrate and very tight bond pad to bond pad spacing on the integrated circuit chip. The pads of the substrate are electrically and physically connected to the bond pads of the integrated circuit chip using fine pitch solder bumps.
These fine pitch solder bumps are delicate and prone to failure due to the differential thermal expansion between the substrate and the integrated circuit chip. More particularly, the load bearing area of the solder bumps is very small and thus the stresses applied thereon are very high due to the thermal expansion mismatch between the integrated circuit chip and the substrate.
To increase the load bearing area of the solder bumps, the diameter of the solder bumps is increased. However, increasing the diameter of the solder bumps decreases the spacing between adjacent solder bumps and between the solder bumps and adjacent traces. Accordingly, the potential for shorting between adjacent solder bumps and between solder bumps and adjacent traces increases.